This invention relates generally to differential amplifiers and more particularly to precision linear differential amplifiers with internal level-shifters, allowing fabrication with only NPN bipolar transistors in the signal path.
A prior art level-shifting amplifier 10 is shown in FIG. 1. The differential amplifier 10 can be fabricated in a semiconductor process that has only NPN bipolar transistors, due to the level-shifting networks. Signal carrying PNP transistors are not required. A main differential amplifier includes transistors Q1 and Q2, load current sources I1 and I2, a gain-setting emitter resistor R1, and a differential input formed by single-ended inputs Inputn and Inputp at circuit nodes 12 and 14. The collector of transistor Q2 is coupled to a level-shifting network including capacitor C1 and resistor R4, and to an input and collector node of an output amplified including transistors Q5 and Q6, current sources I5 and I6, and load resistor R5. An identical level-shifting network including capacitor C2 and resistor R2 is coupled to the collector of transistor Q1. An identical output amplifier includes transistors Q3 and Q4, current sources I3 and I4, and load resistor R3. The differential output for amplifier 10 is formed by the single-ended outputs Outn and Outp of each of the output amplifiers at circuit nodes 16 and 18. The level-shifting networks R2, C2 and R4, C1 shown in amplifier 10 of FIG. 1 are commonly known as an "Addis level-shifters." Each level shifter voltage shifts the output of the main differential amplifier down by a voltage equal to I3.times.R2 and I5.times.R4, which are normally made to be equal. The output voltage can be shifted down to be equal to or less than the input voltage such that numerous stages can be cascaded together without saturation. The operation of amplifier 10 is further described in U.S. Pat. No. 4,725,790 to Addis, which is hereby incorporated by reference.
The main differential amplifier including transistors Q1 and Q2 can be replaced with a Cascomp amplifier, a cascoded amplifier, or one of several other commonly used configurations. The input signal in each of these amplifier configurations generates a signal current through an emitter coupling resistor R1, which in turn flows through transistors Q1 and Q2. In addition, this signal current flows through transistors Q3-Q6 in the output amplifiers. As a result, sufficient standing current must be maintained by current sources I4, I6, I7, and I8 such that the full signal current dynamic range does not shut off any transistor. Typically, current sources I4 and I6 have a value that is slightly more than twice the value of current sources I7 and I8. The bias currents I4 and I6 are set to equally split the current flowing in transistors Q3-Q4 and Q5-Q6 when no signal is applied. In addition to the large standing current requirement of the differential amplifier 10, the level-shifting networks and configuration of the output amplifiers provide no benefit to the linear accuracy of the main amplifier.
Accordingly, a need remains for an all NPN level-shifting differential amplifier having lower standing current requirements and greater linear accuracy that the prior art amplifier shown in FIG. 1.